The present invention relates to methods of manufacturing semiconductor devices and, more specifically, to a method for filling structures with doped or undoped silica glass. It relates to a HDP CVD process used to deposit films (e.g., for IMD, ILD, or STI applications).
It is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio (AR) spaces (AR>3:1) becomes increasingly difficult due to limitations of existing deposition processes. The deposition of doped or undoped silicon dioxide assisted by high density plasma (HDP) chemical vapor deposition (CVD), a directional (bottom-up) CVD process, is the method currently used for high aspect ratio gap-fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. However, there is still formation of overhang at the entry region of the gap to be filled, which results from sputtering and redeposition reactions. The formation of overhang cannot be totally eliminated because non-directional reactions of neutral species and sputtering and redeposition reactions are inherent to the physics and chemistry of the HDP CVD process. However, overhang formation can be minimized by process optimization thus extending the utility of the method.
Several methods have been developed to extend the gap-fill capability of HDP CVD processes (see, for example, U.S. Pat. Nos. 6,030,881, 6,335,261, 6,395,150 and 6,596,654). Previous and current approaches involve the minimization or removal of side-wall overhang by either the use of a surface reactive ambient gas (e.g., hydrogen), or the use of multi-step process schemes including an active etch using a F-based etchant, such as NF3. In many instances, the underlying structure is damaged by the chemical reaction between the gas phase species or simply by excessive sputter etch during the initial stages of the process. For example, in STI structures, a SiN liner is often deposited to enhance electrical isolation between various device elements and improve device performance. The liner can be eroded via several chemical or physical pathways, resulting in compromised device performance (usually demonstrated by higher leakage current).
FIG. 1A shows depicts a damaged STI structure following a conventional HDP CVD gap-fill process. The nitride liner has been damaged or completely removed on the trench sidewall near the trench opening (101), and at the bottom of the trench (103). The potential mechanisms of structure erosion include sputter-etch reactions and ion-assisted reactions, including oxidation via exposure to direct O2 plasma or chemical etch by direct H2 plasma. The result of structure erosion is incomplete electrical isolation between device elements and compromised device performance (a typical manifestation is increased leakage current, resulting in reduced data retention). This, in turn, forces designers to use deeper STI trenches to achieve the necessary level of isolation, which makes the gap-fill problem more severe.
A method is therefore necessary to preserve liner and structure integrity during process initiation and during transitions between process steps in the case of multi-step process schemes.